The present invention relates to an amplifying solid-state image pickup device and a driving method therefor.
Conventionally, there has been proposed an amplifying solid-state image pickup device which has a pixel section having an amplification function and a scanning circuit disposed around the pixel section, where pixel data is read from the pixel section by the scanning circuit. In particular, there has been known an APS (Active Pixel Sensor) type image sensor formed of CMOSs (Complementary Metal Oxide Semiconductor) which are advantageous for integration of the pixel part with peripheral drive circuit and signal processing circuit.
For the APS type image sensor, there is a need for forming a photoelectric conversion part, an amplification part, and a pixel select part and a reset part normally within one pixel. Therefore, in the APS type image sensor, normally, three to four MOS transistors (Tr) are used in addition to the photoelectric conversion part formed of photodiodes (PD).
FIG. 8 shows a construction of an APS type image sensor which employs one photodiode (PD) and four MOS transistors (Tr) to make up a PD+4Tr system. This PD+4Tr system APS image sensor is disclosed in, for example, Reference “I. Inoue et al., IEDM Tech. Digest, pp. 883-886 (1999).”
The APS type image sensor of the PD+4Tr system shown in FIG. 8 is made up of a photodiode 201 as a “PD” and, as the “4Tr,” a transfer transistor 202 for transferring signal charge stored in the photodiode 201, a reset transistor 231, an amplification transistor 232 and a pixel select transistor 233. In this case, assuming that the photodiode 201 is given as buried type and signal charge transfer from the photodiode 201 is perfect, it is known that quite great noise reduction can be achieved and that high-quality images can be obtained.
A drive pulse for the transfer transistor 202 is represented by φT, a drive pulse for the reset transistor 231 is represented by φRR, and a drive pulse for the pixel select transistor 233 is represented by φS. Also, a vertical signal line 235 is grounded via a constant-current load transistor 234 to which a drive pulse φL is applied, where an output signal VS is obtained. In addition, VDD represents a power supply voltage (constant voltage).
FIGS. 9A, 9B, 9C, . . . , 9G are timing charts for explaining circuit operation of the PD+4Tr system APS image sensor shown in FIG. 8.
Drive pulses φR(m), φS(m) and φT(m) for the m-th row (where m is a natural number) and φR(m+1), φS(m+1) and φT(m+1) for the (m+1)th line are repetitions of a similar drive pulse voltage waveform on a basis of one horizontal scan period (1H). Therefore, a description is given below about one horizontal scan period of the m-th row.
First, in a period T1, a drive pulse φR(m) to be applied to the gate of the reset transistor 231 goes High level, where potential level of the gate rises, resulting in an On state of the reset transistor 231. Resultantly, there occurs a charge move from a signal charge storage part 208 to the drain of the reset transistor 231, causing the voltage of the signal charge storage part 208 to be reset to the power supply voltage VDD. In this state, the drive pulse φL applied to the gate of the constant-current load transistor 234 goes High level, resulting in an On state of the constant-current load transistor 234, while the drive pulse φS(m) applied to the gate of the pixel select transistor 233 goes High level, resulting in an On state of the pixel select transistor 233.
In the next period T2, the drive pulse φR(m) applied to the gate of the reset transistor 231 goes Low level, resulting in an Off state of the reset transistor 231. However, because the drive pulse φS(m) applied to the gate of the pixel select transistor 233 is at High level and the pixel select transistor 233 is in the On state, a reset level of the signal charge storage part 208 is read to the vertical signal line 235 via the amplification transistor 232 and the pixel select transistor 233.
In the next period T3, the drive pulse φS(m) applied to the gate of the pixel select transistor 233 goes Low level, resulting in an Off state of the pixel select transistor 233, and the drive pulse φT(m) applied to the gate of the transfer transistor 202 goes High level, where the potential level of the gate rises, resulting in an On state of the transfer transistor 202. Resultantly, the signal charge stored in the photodiode 201 is transferred to the signal charge storage part 208.
In the next period T4, the drive pulse φT(m) applied to the gate of the transfer transistor 202 goes Low level, resulting in an Off state of the transfer transistor 202, while the signal charge storage part 208 is held at the voltage of the transferred signal charge. Then, because the drive pulse φS(m) applied to the gate of the pixel select transistor 233 is at High level and the pixel select transistor 233 is in the On state, a signal level is read to the vertical signal line 235 via the amplification transistor 232 and the pixel select transistor 233. When this occurs, the drive pulse φL applied to the gate of the constant-current load transistor 234 goes High level, resulting in an On state of the constant-current load transistor 234.
For the circuit construction of FIG. 8 and the circuit operation of FIGS. 9A, 9B, 9C, . . . , 9G described above, four transistors and one photodiode are required for each one pixel, which makes a constraint on downsizing of the pixel size. For this reason, there have been made approaches to reduction of the transistor count per pixel.
FIG. 10 shows an amplifying solid-state image pickup device in which a signal charge storage part 208, a reset transistor 231, an amplification transistor 232 and a pixel select transistor 233 are provided in common to a plurality of photodiodes 201 and transfer transistors 202 (see, e.g., JP 09-46596 A).
Operation of the amplifying solid-state image sensor of FIG. 10 is shown in timing charts of FIGS. 11A, 11B, 11C, 11D and 11E.
As shown in FIGS. 11A, 11B, 11C, 11D and 11E, in a period T1, a drive pulse φR(m) applied to the gate of the common reset transistor 231 turns to an On state, where the potential level of the gate rises. Resultantly, there occurs a charge move from the common signal charge storage part 208 to the drain of the common reset transistor 231, causing the voltage of the signal charge storage part 208 to be reset to the power supply voltage VDD. In this state, the drive pulse φL applied to the gate of the constant-current load transistor 234 goes High level, resulting in an On state of the constant-current load transistor 234, while the drive pulse φS(m) applied to the gate of the pixel select transistor 233 goes High level, resulting in an On state of the pixel select transistor 233.
In the next period T2, the drive pulse φR(m) applied to the gate of the common reset transistor 231 goes Low level, resulting in an Off state of the common reset transistor 231. However, because the drive pulse φS(m) applied to the gate of the common pixel select transistor 233 is at High level and the common pixel select transistor 233 is in the On state, the reset level is read to the vertical signal line 235 via the common amplification transistor 232 and pixel select transistor 233.
In the next period T3, the drive pulse φS(m) applied to the gate of the common pixel select transistor 233 goes Low level, resulting in an Off state of the common pixel select transistor 233, and the drive pulse φT(m) applied to the gate of the transfer transistor 202 of the m-th row goes High level, where the potential level of the gate rises, resulting in an On state of the transfer transistor 202. Resultantly, the signal charge stored in the photodiode 201 of the m-th row is transferred to the signal charge storage part 208.
In the next period T4, the drive pulse φT(m) applied to the gate of the transfer transistor 202 of the m-th row goes Low level, resulting in an Off state of the transfer transistor 202, while the common signal charge storage part 208 is held at the voltage of the transferred signal charge. Then, because the drive pulse φS(m) applied to the gate of the common pixel select transistor 233 is at High level and the common pixel select transistor 233 is in the On state, the signal level of the m-th row is read to the vertical signal line 235 via the common amplification transistor 232 and pixel select transistor 233. When this occurs, the drive pulse φL applied to the gate of the constant-current load transistor 234 goes High level, resulting in an On state of the constant-current load transistor 234.
Then, after one horizontal scan period (1H), for pixels of the (m+1)th line, the signal charge is derived from the photodiode 201 of the (m+1)th line via the transfer transistor 202 of the (m+1)th line, where the same operations as in the periods T1 to T4 are performed by the common reset transistor 231, amplification transistor 232 and pixel select transistor 233.
In the construction and operation of the amplifying solid-state image pickup devices shown in FIGS. 10, 11A, 11B, 11C, 11D and 11E, an assumption that one common part is given for two pixels is equivalent to 2.5 transistors per pixel, and an assumption that one common part is given for 4 pixels is equivalent to 1.75 transistors per pixel. That is, in these examples, it becomes achievable to reduce the transistor count per pixel by 1.5 to 2.25.
However, in the construction and operation of the amplifying solid-state image pickup devices shown in FIGS. 10, 11A, 11B, 11C, 11D and 11E, there arise problems as shown below. That is, given that the capacity of the common signal charge storage part 208 is CFD, a charge-voltage conversion efficiency η at which signal charge Qsig derived from the photodiode 201 is converted to a voltage signal Vsig isη=G·Vsig/Qsig=G/CFD   (Eq. 1)where G is the gain of a source follower circuit made up of the amplification transistor 232 and the constant-current load transistor 234, being smaller than 1.
As apparent from Equation 1, the capacity CFD needs to be reduced in order to enlarge the charge-voltage conversion efficiency η. The capacity CFD of the common signal charge storage part 208 is a sum of a drain-side junction capacitance of the transfer transistor 202 and a gate capacitance of the amplification transistor 232, both transistors being connected to the signal charge storage part 208. Therefore, the drain junction capacitance of the transfer transistors increases according as the number of photodiodes and transfer transistors connected to a common signal charge storage part increases, which leads to a problem that the charge-voltage conversion efficiency η decreases.